TigerSharc DSP chips, as high-performance DSP (Digital Signal Processing) chips produced by ADI, have a very high operation processing capacity and execution efficiency as high as 4800 mMACS; and, the main frequency of the processor is as high as 600 MHz, and the on-chip RAM (Random-Access Memory) reaches 24 Mbits. Two independent computing cores are contained in each chip, and up to four instructions may be executed within a clock cycle. This series of chips support multi-DSP co-processing, at most 8 DSPs, and are applicable in the high-speed and high-performance signal processing fields.
Since there is no on-chip non-volatile program memory in TS20x, programs can only be imported into chips from the outside. There are four program downloading modes: PROM boot, Host boot, LinkPort boot and No boot. Among these modes, the PROM boot mode is frequently used, but it is less secure; the LinkPort boot mode is mainly used for downloading programs between DSP chips, low in universality; the No boot mode is mainly used for debugging, which is generally not recommended to use; and, the Host boot mode has a unique advantage in a co-bus system and may use a host to realize the chip boot via an external bus, and this method can realize good compatibility between TigerSharc DSP chips and other systems. However, in the Host boot mode, since the writing sequence of DSPs is strictly required in the booting process, it is error-prone in the booting process. Moreover, for a long boot code, it is time consuming in the Host boot mode.
The conventional Host boot mode for TigerSharc DSP chips is as follows: boot programs are sent to an AUTODMA port (having a fixed address) of the DSPs by using an external bus of the DSPs. The boot programs are received by the AUTODMA port, and the host has the right to control the bus in the boot process. This boot mode can realize the boot of DSPs more flexibly by using the external bus, and is suitable for downloading programs into TigerSharc DSPs via the common external bus by using an FPGA (Field-Programmable Gate Array) or other processors.
However, there still are the following disadvantages in the conventional Host boot mode.
(1) To ensure the boot stability, in the conventional Host boot mode, a delay is to be added after a boot loader and the first five words of the last session are written into TigerSharc DSP chips. Meanwhile, after each Word is written, the next Word can be written only after the DSP has processed the currently written word, and a non-zero code segment and a zero code segment are processed in different time. If the writing speed is too fast, it is very likely to cause the chips to unable to boot. Since the downloading of code contents in code segments takes most of the time of the whole program downloading process, the writing of each Word needs to wait for the response from TigerSharc DSPs. Thus, the quick boot of the TigerSharc DSPs is influenced. A longer code consumes longer boot time.
(2) The data writing is further restricted by an acknowledgement signal ACK, a bus lock signal BUSLOCK and a bus grant signal HBG. The data can be written only when the acknowledgement signal ACK, the bus lock signal BUSLOCK and the bus grant signal HBG are stable, when the boot logics are satisfied and when the TigerSharc DSPs have been prepared. Otherwise, if there is one data lost, the TigerSharc DSPs cannot be booted.